The present invention relates to a full adder applied to an operation circuit or the like.
FIG. 1 shows a conventional full adder which is composed of complementary MOSFETs. This full adder is described on PP. 51-54 of Proceedings of the conference on Solid State Devices, Tokyo, 1981; JJAP, vol. 21 (1982) Supplement 21-1. The full adder has p-channel MOSFETs P1 to P14 and n-channel MOSFETs N1 to N14. Reference symbols XO, YO and ZO denote input signals; CO, a carry output signal; SO, a sum output signal. The carry output signal CO and the sum output signal SO are given by the following relations: EQU SO=XO.sym.YO.sym.ZO EQU CO=XO.multidot.YO+YO.multidot.ZO+ZO.multidot.XO
where symbol .sym. denotes the exclusive OR, a point denotes the logical AND, and symbol + denotes the logical OR.
The conventional full adder with the arrangement shown in FIG. 1 has a disadvantage in that the number of elements is increased since 28 MOSFETs are used. Therefore, the chip size is increased when an adder is integrated.